As semiconductor design rules become smaller, integrated circuits occupy less substrate area. In general, smaller integrated circuits typically form faster devices and have higher substrate yields. Memory devices, which are a type of integrated circuit, need to have their memory cell area minimized. Memory cell area is a function of among other things, the design rules and the memory cell layout. Smaller design rules cannot overcome inherent limitations that exist with an inefficient memory cell layout. More efficient use of substrate area is needed to improve the performance and yield of the integrated circuit. A static random access memory is a type of device that may include a memory array with memory cells each having two pass transistors, two latch transistors, and two load transistors. Preferably, the pass transistors have similar electrical characteristics to one another, the latch transistors have similar electrical characteristics to one another, and the load transistors have similar electrical characteristics to one another. A symmetric memory cell layout is one way of achieving similar electrical characteristics between the three pairs of transistors within the memory cell. Therefore, a small memory cell area is needed, and the memory cell layout should be symmetrical.
One attempt to reduce memory cell area and still have a symmetric memory cell layout is to split the word line over the memory cell. Regardless of the design rules, the amount of substrate area occupied by the split word line memory cell is inherently limited by the memory cell layout. Pass and latch transistors within a memory cell typically have about the same gate dielectric layer thickness. Because the ratio of the gain of the latch transistors to the gain of the pass transistors is typically greater than 1:1, the pass transistors typically have a large channel width to channel length ratio. The large channel width to channel length ratio typically occupies a large memory cell area.